Method and system for reducing program code size

ABSTRACT

In a method for reducing code size a replaceable subset of instructions at a first location within a set of instructions and a matching target subset of instructions at a second location within the set of instructions are identified. A base offset and a relative offset are determined. The base offset and the relative offset indicate an absolute offset from the first location to the second location. An instruction to cause a base offset storage element to be loaded with the base offset is inserted prior to the first location. The replaceable subset of instructions is replaced with a second instruction to cause a program counter to be modified based on the relative offset and a value in the base offset register so that the modified program counter indicates the second location.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. patent application Ser. No. ______(attorney docket no. 30320/21141), entitled “METHOD AND SYSTEM FORREDUCING PROGRAM CODE SIZE,” filed on the same day as the presentapplication, and is hereby incorporated by reference herein in itsentirety for all purposes.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to computer systems and moreparticularly to methods and systems for reducing the size of a programto be executed by a computer system.

BACKGROUND

In some computer systems, the size of a program to be executed may besubject to constraints. For example, the computer system may have alimited amount of memory in which to store the program. Techniques havebeen developed to compress the size of a program.

For example, one technique, often referred to as “Echo Technology,”replaces a set of instructions in a program with a single “EchoInstruction” which typically have the format “Echo (offset, length)”.The “offset” parameter may specify an offset between a location of areplaceable set of instructions (to be replaced by the single EchoInstruction) and a location of a target set of instructions that matchthe instructions in the replaceable set. The “length” parameter mayspecify a number of instructions in the replaceable set of instructions.When the Echo Instruction is executed, the “offset” parameter is used tocause control to branch to the location of the target set ofinstructions. Then, the processor begins to execute the instructions inthe target set. The “length” parameter is used to determine when controlshould branch back to the instruction immediately following the EchoInstruction. Because many instructions can be replaced by a smallernumber of Echo Instructions, this technique may help to reduce the sizeof a program.

An illustrative example will be described with reference to Tables 1 and2. Table 1 lists instructions and their locations in an example set ofprogram code. The set of instructions at locations 340 to 356 matchesthe set of instructions at locations 100 to 116. Thus, the instructionsat locations 340 to 356 can be replaced by an Echo Instruction whichinducates an offset of 240 (340 minus 100) and a length of 5. Theinstructions at locations 340 to 356 can be referred to as a replaceableset of instructions. Table 2 shows a list of instructions in which theinstructions at locations 340 to 356 have been replaced by an EchoInstruction that indicates an offset of 240 and a length of 5. Thus, theEcho Instruction at location 340 points to the five instructionsstarting at the location 100, which may be referred to as a target setof instructions. TABLE 1 Location Instruction 100 mov 104 shl 108 xor112 add 116 movsx . . . . . . 340 mov 344 shl 348 xor 352 add 356 movsx. . . . . . 404 mov 408 shl 412 xor 416 add 420 movsx . . . . . .

TABLE 2 Location Instruction 100 mov 104 shl 108 xor 112 add 116 movsx .. . . . . 340 Echo(240, 5) . . . . . . 388 mov 392 shl 396 xor 400 add404 movsx . . . . . .

Because the five instructions at locations 340 to 356 have been replacedby a single Echo Instruction, the instructions that were at locations404 to 420 (in Table 1) will now be at the locations 388 to 404 (Table2). These instructions also match the set of instructions at locations100 to 116. Thus, the instructions at locations 388 to 404 can bereplaced by an Echo Instruction which indicates an offset of 288 (388minus 100) and a length of 5. Table 3 shows a list of instructions inwhich the instructions at locations 388 to 404 have been replaced by anEcho Instruction that indicates an offset of 288 and a length of 5.Thus, the Echo Instruction at location 388 points to the fiveinstructions starting at the location 100. TABLE 3 Location Instruction100 mov 104 shl 108 xor 112 add 116 movsx . . . . . . 340 Echo(240, 5) .. . . . . 388 Echo(288, 5) . . . . . .

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an example system for generating machineexecutable code from source code.

FIG. 2 is a flow diagram of an example method for compressing code thatmay be implemented by a system such as the system of FIG. 1.

FIG. 3 is a flow diagram of another example method for compressing codethat may be implemented by a system such as the system of FIG. 1.

FIG. 4 is an example routine, in pseudocode, for implementing a portionof the method of FIG. 3.

FIG. 5 is another example routine, in pseudocode, for implementing aportion of the method of FIG. 3.

FIG. 6 is another example routine, in pseudocode, for implementing aportion of the method of FIG. 3.

FIG. 7 is a block diagram of another example system for generatingmachine executable code from source code.

FIG. 8 is flow diagram of an example method for compressing code thatmay be implemented by a system such as the system of FIG. 7.

FIG. 9 is an example routine, in pseudocode, for implementing a portionof the method of FIG. 8.

FIG. 10 is block diagram of an example subsystem of a processorconfigured to execute instructions that cause a program counter to bemodified based on a relative offset and a base offset.

FIG. 11 is a flow diagram of an example method for, in response to aninstruction at a first location, executing a set of instructions at asecond location indicated by the instruction at the first location.

FIG. 12 is a block diagram of an example computing device that may beemployed to compress code and/or execute code that includes aninstruction at a first location to cause execution of a set ofinstructions at a second location.

DETAILED DESCRIPTION

FIG. 1 is a block diagram of an example system 100 for generatingmachine executable code 104 from source code 108. The system 100 alsoattempts to reduce the size of the executable code 104 by utilizing EchoInstructions. Further, the system 100 attempts to improve performance ofthe compressed executable code 104 by utilizing Echo Instructions thatpoint to target code in areas that are frequently executed.

The system 100 includes a compiler 112 that compiles the source code 108into object code 116. The system also includes a linker 120 thatgenerates the executable code 104 from the object code 116. The system100 additionally includes a code compressor 124 that compresses theobject code 116. In particular, the code compressor 124 identifiesreplaceable sets of instructions in areas of the code that have beendetermined to be infrequently executed (hereinafter referred to as “coldareas”) and target sets of instructions that match the replaceable setsof instructions. The code compressor 124 may store indications ofmatches of replaceable sets of instructions with target sets ofinstructions as optimization information 128. The optimizationinformation 128 may also include information that identifies the coldareas in the object code 116, and may further include information thatidentifies areas of code that have been determined to be frequentlyexecuted (hereinafter referred to as “hot areas”). A variety oftechniques, including techniques known to those of ordinary skill in theart, may be used to identify cold areas and hot areas of the code. Forexample, a variety of code profiling techniques may be used to identifycold areas and hot areas of the code. The code compressor 124 mayreplace some or all of the replaceable sets of instructions with EchoInstructions.

The system 100 further includes a code reorderer 132 that rearranges theobject code 116. For example, the code reorderer 132 may attempt torearrange cold areas and hot areas in the object code in an attempt toreduce offsets between the replaceable sets of instructions and thematching target sets of instructions.

The source code 108 may include computer program instructions written ina variety of programming languages such as C language, C++ language, C#language, FORTRAN language, etc. The compiler 112 may comprise anysuitable compiler including compilers known to those of ordinary skillin the art. The linker 120 may comprise any suitable linker includinglinkers known to those of ordinary skill in the art. The executable code104 may include machine executable code executable by a variety ofprocessors including currently available processors and processors notyet developed. In some implementations, the linker 120 may be omitted.In these implementations, the object code 116 may comprise machineexecutable code.

In another implementation, the source code 108 may include computerprogram instructions written in one of a variety of assembly languages.In this implementation, the compiler 112 may be replaced by any suitableassembler including assemblers known to those of ordinary skill in theart. In general the instructions operated upon by the code compressor124 and the code reorderer 132 may be generated from source code usingany suitable system for converting source code into object code and/ormachine executable code.

In another implementation, the code compressor 124 and the codereorderer 132 may operate on the machine executable code 104 rather thanthe object code 116.

FIG. 2 is a flow diagram of an example method 160 for compressing codethat may be implemented by a system such as the system 100 of FIG. 1.The flow of FIG. 2 will be explained with reference to FIG. 1. At ablock 164, replaceable sets of instructions in cold areas and targetsets of instructions that match the replaceable sets of instructions areidentified. For example, the code compressor 124 may identify thereplaceable sets and target sets. Any number of techniques can be usedto identify the replaceable and target sets. For example, techniquesknown to those of ordinary skill in the art can be modified to identifymatching first and target sets of instructions where the replaceablesets of instructions are in cold areas.

The first and target sets of instructions may be identified subject toone or more constraints in addition to the instructions in thereplaceable and target sets matching and that the replaceable sets arein cold areas. For example, one constraint may be that each replaceableset of instructions must be less than or equal to a maximum length. Asdiscussed previously, some Echo Instructions have the format “Echo(offset, length)”, where the “length” parameter specifies a number ofinstructions in the replaceable set of instructions. The format of theEcho Instruction may allocate a certain number of bits to the “length”parameter, thus dictating a maximum value of the length parameter. Thismaximum value of the length parameter may correspond to the maximumlength of each replaceable set of instructions. Additionally, someimplementations may include several Echo Instructions each having adifferent instruction length and/or format. This may allow, for example,different Echo instructions to have “offset” and/or “length” parametershaving differing numbers of bits. In such implementations, the maximumlength of each replaceable set of instructions may correspond to theEcho Instruction “length” parameter having the largest number of bits.

Another example of an optional constraint is that only replaceable setsare identified that, when replaced with Echo Instructions, result in asmaller size code. For instance, if a replaceable set is too small insize, replacing it with an Echo Instruction may actually increase thesize of the code.

If more than one target set is identified for a replaceable set at theblock 164, one target set is chosen, at a block 168, such that targetsets in hot areas are favored over target sets in cold areas. Forexample, if a target set in a hot area and a target set in a cold areaboth match a replaceable set, the target set in the hot area will bechosen. Additional criteria may optionally be used to choose a targetset from a plurality of matching sets. For example, offsets between thereplaceable set and respective target sets may optionally be used tochoose one of the target sets. For instance, if two or more target setsin hot areas match, the target set with the smallest offset to thereplaceable set may optionally be chosen. Alternatively, the firstidentified or the last identified target set in a hot area may bechosen. The code compressor 124 may choose the one target set and maydetermine whether a particular target set is in a cold area or a hotarea based on cold/hot area information in the optimization information128.

At a block 172, code regions may be reordered in an attempt to reduceoffsets between the replaceable sets and their matching target sets. Anynumber of techniques, including techniques known to those of ordinaryskill in the art, may be used. In one implementation, for example, agraph optimization technique is used in which a graph is built havingcode areas as nodes, and edges between the nodes having weights based onthe offsets between matching replaceable set and target set pairs.Optionally, the weights may also be based on the sizes of the matchingreplaceable set and target set pairs. Then, the graph may be linearizedso that a total weighted linear distance is minimized. A graph reductiontechnique, for example, may be used to linearize the graph. Examples ofother techniques known to those of ordinary skill in the art that can beused to reorder code regions to attempt to reduce offsets includeinteger programming techniques and exhaustive search techniques.

At a block 176, at least some of the replaceable sets of instructionsidentified at the block 164 are replaced with Echo Instructions. Forexample, the code compressor 124 may replace at least some of thereplaceable sets of instructions with Echo Instructions. As discussedabove, some implementations may include several Echo Instructions eachhaving a different instruction length and/or format. This may allow, forexample, different Echo instructions to have “offset” and/or “length”parameters having differing numbers of bits. In these implementations, areplaceable set may optionally be replaced with the shortest EchoInstruction possible given the length of the replaceable set and theoffset from the replaceable set to the matching target set.

FIG. 3 is a flow diagram of another example method 200 for compressingcode that may be implemented by a system such as the system 100 ofFIG. 1. The flow of FIG. 3 will be explained with reference to FIG. 1.The blocks 164, 168, and 172 are the same as in FIG. 2. After the block172, at a block 204, replaceable sets of instructions in cold areas andtarget sets of instructions that match the replaceable sets ofinstructions are again identified. Identifying the replaceable andtarget sets may be implemented in a manner similar to the block 204. Thefirst and target sets of instructions may be identified at the block 204with or without using information from the identification of such setsat the block 164.

If more than one target set is identified for a replaceable set at theblock 204, one target set is chosen, at a block 208, such that targetsets in hot areas are favored over target sets in cold areas. Choosing atarget set may be implemented in the same or similar manner as the block168. The same criteria or different criteria as used at the block 168may be used at the bock 208.

At the block 212, at least some of the replaceable sets of instructionsidentified at the block 164 are replaced with Echo Instructions. Theblock 212 may be implemented in a manner similar to or the same as theblock 176 of FIG. 2.

FIG. 4 is an example routine 220, in pseudocode, for implementing theblocks 164 and 168 of FIG. 3. An input to the routine 220 is the datastructure “code”, which includes a plurality of instructions to becompressed. The data structure “code” may be of the form: structProcessedInst { char size; char *abs_bits; char is_br_target; charis_non_echoable; char is_echo; unsigned compressed_pc; };The “size” field indicates the number of bytes of a particularinstruction in the array. The “abs_bits” field is a pointer to decodedbits corresponding to the instruction, with PC-relative addressesreplaced by absolute addresses. The “is_br_target” field indicateswhether or not the current instruction is a target of a branch. The“is_non_echoable” field indicates that the instruction should not be ina replaceable set of instructions that can be replaced by an EchoInstruction. The “is_echo” field is used to indicate a first instructionin a set of instructions that is to be replaced by an Echo Instruction.The “compressed_pc” field indicates a program counter corresponding tothe instruction after previous instructions have been replaced by EchoInstructions. The “compressed_pc” field of the first instruction in thestructure is zero.

An i-loop of the routine 220 examines cold areas of the instructions,starting at code[i], and a j-loop examines both hot and cold areas fromcode[0] to code[i−1], in an attempt to find replaceable sets ofinstructions that match target sets of instructions. A function“is_in_hot_area(i)” determines whether the instruction code[i] is in ahot area.

A function “is_non_echoable_inst(i)” determines whether the instructioncode[i] can be replaced by an Echo Instruction. For example, in someimplementations, it may be decided that certain instructions should notbe replaced by an Echo Instruction. For instance, it may be decided thatif a set of instructions includes an instruction that is a target of abranch instruction and if that instruction is not the first instructionin the set of instructions, the set of instructions should not bereplaced by an Echo Instruction. As another example, it may be decidedthat if a set of instructions includes looping or branchinginstructions, the set of instructions should not be replaced by an EchoInstruction.

A function “is_inst_match(j, i) determines if the instruction at code[i]matches the instruction at code[j ]. A function“is_better_candidate(prev_region_size, prev_target, cur_region_size,cur_target) determines whether a current potential target set ofinstructions is better than a previously identified potential target setof instructions. Typically, if two potential target sets of instructionsboth match instructions starting at code[x], but one of the potentialtarget sets is longer, the longer of the two potential target sets isconsidered “better.” Also, if two potential target sets of instructionshave the same length, but one is in a hot area and the other is in acold area, the potential target set in the hot area is considered“better.”

A function “record_echo_region_and_target(echo_region, region_size,echo_target) records information regarding the identified replaceableset of instructions and the chosen target sets of instructions thatmatch the replaceable sets.

FIG. 5 is an example routine 240, in pseudocode, for implementing theblock 172 of FIG. 3. An input to the routine 240 is a set of code areasthat can be reordered, a list of replaceable sets of instructions andmatching target sets of instructions generated at the blocks 164 and168. The routine 240 builds a graph with the code areas as nodes and theweight on a directed edge A1->A2 indicates how important that area A1should be placed immediately before area A2. Once the graph is built, itmay be linearized so that the total weighted linear distance isminimized. The routine may use a graph reduction technique, for example,to linearize the graph.

FIG. 6 is an example routine 260, in pseudocode, for implementing theblocks 204, 208, and 212 of FIG. 3. The routine 260 is similar to theroutine 220 of FIG. 4. A routine get_earlest_inst(i) finds an earliestinstruction index, early_index, such that the difference between thecode[i].compressed_pc and code[early_index].compressed_pc is less thanor equal to a maximum offset supported by a processor architecture. Afunction “region_may_not_be_echoed(region_size, region_inst, offset, &best_echo_inst_size)” determines if a candidate replaceable set ofinstructions can be beneficially replaced by an Echo Instruction takinginto consideration criteria such as processor architecture limitations.For example, a candidate replaceable set of instructions could be toosmall such that replacing it with any Echo Instruction may increase thecode size. If the candidate replaceable set of instructions can bereplaced by any of multiple Echo Instructions, a smallest EchoInstruction is chosen and the corresponding Echo Instruction size isreturned in the variable best_echo_inst_size. A routine“replace_region_by_echo_inst(region_begin, region_end, echo_inst_size)”will replace the replaceable set of instructions by the selected EchoInstruction. In this event, the “size” field for the first instructionin the set to be replaced is set to the size of the Echo Instruction,and the “size” fields for the other instructions in the set are set tozero. Additionally, the “compressed_pc” fields for the instructions inthe set replaced by the Echo Instruction are updated.

FIG. 7 is a block diagram of another example system 300 for generatingmachine executable code 104 from source code 108. The system 300 alsoattempts to reduce the size of the executable code 104 utilizing adifferent type of Echo Instruction as will be described below.

Similar to the system 100 of FIG. 1, the system 300 includes a compiler112 that compiles the source code 108 into object code 116. The system300 also includes a linker 120 that generates the executable code 108from the object code 116. The system 300 additionally includes a codecompressor 304 that compresses the object code 116. In particular, thecode compressor 304 identifies replaceable sets of instructions andtarget sets of instructions that match the replaceable sets ofinstructions. The code compressor 304 may store indications of matchesof replaceable sets of instructions with target sets of instructions asoptimization information 308.

In the example system 300, the code compressor 304 utilizes instructionshaving a format such as the format “Echo(relative_offset, length)”. Suchinstructions will be referred to hereinafter as Relative Offset EchoInstructions. Relative Offset Echo Instructions are similar to the EchoInstruction described above, but the offset from the Relative OffsetEcho Instruction to the target set of instructions is determined byadding the relative_offset to a base_offset. The base_offset may be setusing an instruction having a format such as the format“setEchoBase(base_offset)”. Such instructions will hereinafter bereferred to as Set Echo Base Instructions. The Relative Offset EchoInstructions may be made smaller than the Echo Instructions describedpreviously because the relative offsets will tend to be smaller than theabsolute offset. Thus, a smaller number of bits are required torepresent a relative offset as opposed to an absolute offset. On theother hand, additional Set Echo Base Instructions are required to beinserted in the code. On the whole, however, the use of Relative OffsetEcho Instructions may lead to a smaller code size as compared to theEcho Instructions described previously.

In another implementation, the code compressor 304 may operate on themachine executable code 104 rather than the object code 116.

FIG. 8 is flow diagram of an example method 350 for compressing codethat may be implemented by a system such as the system 300 of FIG. 7.The flow of FIG. 8 will be explained with reference to FIG. 7. At ablock 354, a replaceable set of instructions and a target set ofinstructions that match the replaceable set are identified. For example,the code compressor 304 may identify the replaceable set and target set.Any number of techniques, including techniques known to those ofordinary skill in the art, can be used to identify the replaceable andtarget sets. The block 354 may comprise choosing one target set ifmultiple matching target sets are identified. For example, a matchingtarget set having a smallest offset to the replaceable set may bechosen. Other criteria for selecting one target set from a plurality ofmatching target sets may be used additionally or alternatively.

At a block 358, a base offset and a relative offset are determined forthe replaceable set of instructions and the matching target set ofinstructions. For example, the code compressor 304 may determine thebase offset and relative offset. A variety of techniques for determiningthe base offset and relative offset may be used. For example, anabsolute offset may first be determined, and then a base offset and arelative offset may be determined using the absolute offset. In oneimplementation, multiple absolute offsets corresponding to multiplepairs of replaceable sets and target sets are first determined. Then, abase offset is determined for the multiple pairs of replaceable sets andtarget sets. Next, relative offsets for the multiple pairs ofreplaceable sets and target sets are determined by subtracting the baseoffset from each of the absolute offsets.

At a block 362, a Set Echo Base Instruction is inserted in the codeprior to the replaceable set of instructions to set a register, forexample, of a processor with the base offset value determined at theblock 358. Because the base offset will often be the same for multiplematching pairs of replaceable sets and target sets, the block 362 mayneed to be performed only once for a plurality of matching replaceablesets and target sets of instructions. The code compressor 304, forexample, may insert the Set Echo Base Instruction.

At a block 366, the replaceable set of instructions is replaced by aRelative Offset Echo Instruction. The code compressor 304, for example,may insert the Relative Offset Echo Instruction. The block 366 maycomprise selecting one Relative Offset Echo Instruction from a pluralityof possible Relative Offset Echo Instructions. For example, a shortestRelative Offset Echo Instruction may be selected. Other criteria may beused additionally or alternatively. The order of the blocks 362 and 366may be reversed in some implementations.

In another example, a processor architecture may include multiple baseoffset registers. In this example, a block may be included in the method350 to select an appropriate Set Echo Base Instruction to set anappropriate one of the multiple base offset registers with the baseoffset value determined at the block 358. Additionally, a RelativeOffset Echo Instruction may include a parameter that indicates anappropriate one of the multiple base offset registers to use. Similarly,opcodes of multiple Relative Offset Echo Instructions may each indicatean appropriate one of the multiple base offset registers to use.

FIG. 9 is an example routine 400, in pseudocode, for implementing theblocks 354, 358, 362, and 366 of FIG. 8. An input to the routine 400 isthe data structure “code”, which includes a plurality of instructions tobe compressed. The routine 400 replaces sets of instructions with one ofa plurality of Relative Offset Echo Instructions supported by aparticular processor architecture. The routine 400 also inserts Set EchoBase Instructions at appropriate places in the code. The routine 400 issimilar to the routine 260 of FIG. 6.

An i-loop of the routine 400 examines instructions, starting at code[i],and a j-loop examines instructions from code[0] to code[i−1], in anattempt to find replaceable sets of instructions that match target setsof instructions. A function “is_non_echoable_inst(i)” determines whetherthe instruction code[i] can be replaced by an Echo Instruction or aRelative Offset Echo Instruction. A routine get_earlest_inst(i) finds anearliest instruction index, early_index, such that the differencebetween the code[i].compressed_pc and code[early_index].compressed_pc isless than or equal to a maximum offset supported by a processorarchitecture.

A function “is_inst_match(j, i) determines if the instruction at code[i]matches the instruction at code[j]. A function“is_better_candidate(prev_region_size, prev_target, cur_region_size,cur_target) determines whether a current potential target set ofinstructions is better than a previously identified potential target setof instructions. Typically, if two potential target sets of instructionsboth match instructions starting at code[x], but one of the potentialtarget sets is longer, the longer of the two potential target sets isconsidered “better.”

A function “region_may_not_be_echoed(region_size, region_inst, offset, &best_echo_inst_size)” determines if a candidate replaceable set ofinstructions can be beneficially replaced by an Echo Instruction or aRelative Offset Echo Instruction, taking into consideration criteriasuch as processor architecture limitations. For example, a candidatereplaceable set of instructions could be too small such that replacingit with any Echo Instruction or Relative Offset Echo Instruction mayincrease the code size. If the candidate replaceable set of instructionscan be replaced by one of a plurality of Echo Instructions, a smallestEcho Instruction may be chosen and the corresponding Echo Instructionsize is returned in the variable best_echo_inst_size. A routinereplace_region_by_echo_inst(region_begin, region_end, echo_inst_size)replaces the current replaceable set of instructions by an Echoinstruction and also updates the compressed_pc field for theinstructions in the replaceable set of instructions.

Finally, a boost_echos( ) routine processes the Echo Instructions thathave been inserted in the code and attempts to reduce the size of thecode by replacing Echo Instructions with Relative Offset EchoInstructions and inserting Set Echo Base Instructions. Any of a varietyof techniques may be used to attempt to reduce the size of the code. Forexample, Echo Instructions in each function of the code could beanalyzed as a group. A function may have a number t of Echo Instructionswith the sizes s₁, s₂, . . . , s_(t). If the Echo Instructions arereplaced by Relative Offset Echo Instructions, the relative_offsetparameters corresponding to these instructions may be reduced bysubtracting a base offset B, and thus fewer bits may be needed torepresent the smaller relative_offset parameters as compared to theabsolute offsets. Thus, it may be possible to replace some or all of theEcho Instructions in the function, if an appropriate Set Echo BaseInstruction is inserted previous to these instructions, such thatRelative Offset Echo Instructions in the function have sizes n₁, n₂, . .. , n_(t). If the Set Echo Base Instruction has a size of S bits, it maybe beneficial to insert the Set Echo Base Instruction and replace theRelative Offset Echo Instructions in the function if${\sum\limits_{i = 1}^{t}\left( {s_{i} - n_{i}} \right)} > {S.}$A Set Echo Base Instruction may be inserted in a function prolog, forexample.

In another implementation, Echo Instructions are not first inserted andthen replaced by Relative Offset Echo Instructions. Rather, RelativeOffset Echo Instructions are directly inserted along with Set Echo BaseInstructions.

FIG. 10 is block diagram an example subsystem 450 of a processorconfigured to execute instructions that cause a program counter to bemodified based on a relative offset and a base offset. In general, anyof a variety of processors may be designed to include a subsystem suchas the subsystem 450. For example, processors such as processors sold byIntel® (e.g., any of the Pentium® family, the Itanium™ family and/or theIntel XScale® family of processors) could be modified. Other types ofprocessors and processors sold by other companies could be similarlymodified. For example, a micro signal architecture (MSA) processor, adigital signal processor (DSP), a pipelined processor, a complexinstruction set computer (CISC) processor, a reduced instruction setcomputer (RISC) processor, an explicitly parallel instruction computing(EPIC) processor, a very long instruction word (VLIW) processor, or anyother type of processor could be modified to include a subsystem such asthe subsystem 450.

The subsystem 450 includes an instruction decode unit 454 configured todecode Relative Offset Echo Instructions and Set Base Offset EchoInstructions. The subsystem 450 also includes a storage element 458(e.g., a register), coupled to the instruction decode unit 454, to storea base offset. The instruction decode unit 454 may generate a baseoffset value by decoding a Set Echo Base Instruction, for example. Also,the instruction decode unit 454 may generate one or more control signals(not shown) to cause the base offset value to be loaded into the storageelement 458 in response to a Set Echo Base Instruction.

The subsystem 450 also includes an adder 462 coupled to the instructiondecode unit 454. The adder 462 subtracts from a current program counter(PC) the value stored in the storage element 458 and a relative offsetvalue received from the instruction decode unit 454. The instructiondecode unit 454 may generate the relative offset value by decoding aRelative Offset Echo Instruction.

The subsystem 450 also includes a storage element 466 (e.g., a register,a counter, etc.) for storing the PC. The storage element 466 may becoupled to an output of the adder 462 via a multiplexer 470. Themultiplexer 470 may be used to load different values into the storageelement 466. The storage element 466 also may be coupled to an input ofthe adder 462 to provide a current PC value to the adder 462.

In response to a Relative Offset Echo Instruction, the instructiondecode unit 454 may generate one or more control signals (not shown) tocause the multiplexer 470 to select the output of the adder 462 to beprovided to the storage element 466. Also, the instruction decode unit454 may generate one or more control signals (not shown) to cause thestorage element 466 to load the output of the adder 462.

The subsystem 450 may optionally include a multiplexer 474 to select, asan input to the adder 462, an output of the storage element 458 or thevalue zero. If the instruction decode unit 454 is configured to decodeprior art Echo Instructions, the instruction decode unit 454 maygenerate one or more control signals (not shown) to cause themultiplexer 474 to select the value zero. Additionally, instructiondecode unit 454 may cause the absolute offset specified by the EchoInstruction to be provided as an input of the adder 462. Alternatively,the multiplexer 474 may be omitted, and the output of the storageelement 458 may be coupled to the adder 462.

In another example, the subsystem 450 may include multiple storageelements 458 for storing multiple base offsets. In this example, eachSet Echo Base Instruction may indicate the particular storage element458 that is to be loaded. For example, a Set Echo Base Instruction mayinclude a parameter to indicate the particular storage element 458 thatis to be loaded. As another example, multiple Set Echo Base Instructionsmay be provided, wherein each opcode of the Set Echo Base Instructionsindicates a corresponding storage element 458 that is to be loaded.

Similarly, each Relative Offset Echo Instruction may indicate theparticular storage element 458 that is to be used in generating theabsolute offset. In this example, the multiplexer 474 could be modifiedto provide one base offset value from the plurality of storage elements458 to the adder 462. The instruction decode unit 454 may generate oneor more control signals to control the multiplexer 474 to select anappropriate base offset value from the plurality of storage elements458. The Relative Offset Echo Instruction may include a parameter toindicate the particular storage element 458 that is to be used. Asanother example, multiple Relative Offset Echo Instructions may beprovided, wherein each opcode of the Relative Offset Echo Instructionsindicates a corresponding storage element 458 that is to be used.

The instruction decode unit 454 may be configured as described aboveusing any number of techniques, including techniques known to those ofordinary skill in the art. For example, the instruction decode unit 454could be implemented using hardware.

FIG. 11 is a flow diagram of an example method 500 for, in response toan instruction (e.g., a Relative Offset Echo Instruction) at a firstlocation, executing a set of instructions (e.g., a target set) at asecond location indicated by the instruction at the first location. Themethod 500 may be implemented using a subsystem such as the system 450of FIG. 10, for example. In general, the method 500 can be implementedby a suitably configured processor. Processors that could be modified toimplement the method 500 include processors sold by Intel® (e.g., any ofthe Pentium® family, the Itanium™ family and/or the Intel XScale® familyof processors), similar processors sold by other companies, an MSAprocessor, a DSP, a pipelined processor, a CISC processor, a RISCprocessor, an EPIC processor, a VLIW processor, etc.

At a block 502, an ECHO_MODE flag should be set to indicate that theinstructions being executed are in response to a Relative Offset EchoInstruction or an Echo Instruction. At a block 504, a RETURN_PC value iscalculated as the current PC plus the size of the Relative Offset EchoInstruction. At a block 508, the PC is modified by subtracting therelative and base offsets. The relative offset is indicated by theRelative Offset Echo Instruction, whereas the base offset is a valuestored in an appropriate base offset register. At a block 512, anECHO_COUNTER is set to a length value indicated by the Relative OffsetEcho Instruction.

At a block 516, an instruction indicated by the PC is executed. If theinstruction is a CALL-type instruction, the following values should besaved and then restored on return: ECHO_MODE, RETURN_PC, ECHO_COUNTER,and BASE_OFFSET. At a block 520, the PC is updated to point to a nextinstruction. At a block 524, the ECHO_COUNTER is decremented. At a block528, it is checked whether the ECHO_COUNTER is zero. If the ECHO_COUNTERis not zero, the flow returns to the block 516. If the ECHO_COUNTER iszero, the PC is set to the RETURN_PC at a block 532. At a block 526, theECHO_MODE flag is cleared.

A processor architecture may support one or more Relative Offset EchoInstructions. For example, if a Relative Offset Echo Instructionincludes a relative offset parameter and a length parameter, multipleRelative Offset Echo Instructions may be supported that correspond todifferent bit length relative offset parameters and length parameters.In one implementation, Relative Offset Echo Instructions having one-byteopcodes and two-byte opcodes such as the instructions listed in Tables 3and 4 are supported. TABLE 3 One-byte Opcodes Bit-length of RelativeOffset Bit-length of Length Instruction Parameter Parameter Instruction#1 8 0 Instruction #2 7 1 Instruction #3 14 2 Instruction #4 20 4

TABLE 4 Two-byte Opcodes Bit-length of Relative Offset Bit-length ofLength Instruction Parameter Parameter Instruction #5 8 0 Instruction #67 1 Instruction #7 14 2 Instruction #8 20 4

It is to be understood that the Relative Offset Echo Instructions listedin Tables 3 and 4 are merely illustrative examples of Relative OffsetEcho Instructions that may be supported by a processor architecture. Aparticular architecture may support different Relative Offset EchoInstructions. For example, different length opcodes and differentbit-length parameters may be supported. Similarly, differentcombinations of relative offset and length parameter bit-lengths may besupported. Additionally, some or all Relative Offset Echo Instructionsmay incorporate the relative offset parameter and/or the lengthparameter into the opcode. Further, if a processor includes multiplebase offset registers, Relative Offset Echo Instructions may include aparameter to indicate an appropriate base offset register. Similarly,some or all Relative Offset Echo Instructions may incorporate anindication of the appropriate base offset register into the opcode.

FIG. 12 is a block diagram of an example computing device 600 that maybe employed to compress code and/or execute code that includes EchoInstructions and/or Relative Offset Echo Instructions. It is to beunderstood that the computing device 600 illustrated in FIG. 12 ismerely one example of a computing device that may be employed. Asdescribed above, many other types of computing devices may be used aswell. The computing device 600 may include at least one processor 604, avolatile memory 608, and a non-volatile memory 612. The processor may ormay not be configured to execute one or more of an Echo Instruction, aRelative Offset Echo Instruction, and a Set Echo Base Instruction. Thevolatile memory 608 may include, for example, a random access memory(RAM). The non-volatile memory 612 may include, for example, one or moreof a hard disk, a read-only memory (ROM), a CD-ROM, an erasableprogrammable ROM (EPROM), an electrically erasable programmable ROM(EEPROM), a digital versatile disk (DVD), a flash memory, etc. Thecomputing device 600 may also include an I/O device 616. The processor604, volatile memory 608, non-volatile memory 612, and the I/O device616 may be interconnected via one or more address/data buses 620. Insome embodiments, one or more of the volatile memory 608, non-volatilememory 612, and the I/O device 616 may be coupled to the processor 604via one or more separate address/data buses (not shown) and/or separateinterface devices (not shown), coupled directly to the processor 604,etc.

The computing device 600 may also include at least one display 624 andat least one user input device 628. The user input device 628 mayinclude, for example, one or more of a keyboard, a keypad, a mouse, atouch screen, etc. Additionally, the computing device 600 may alsoinclude a network interface device 632 to couple the computing device600 to a network such as a local area network, a wide area network, awireless network, the Internet, etc.

The display 624, the user input device 628, and the network interfacedevice 632 are coupled with the I/O device 616. Although the I/O device616 is illustrated in FIG. 12 as one device, it may comprise severaldevices. Additionally, in some embodiments, one or more of the display624, the user input device 628, and the network interface 632 may becoupled directly to the address/data bus 620 or the processor 604.

Referring again to FIGS. 1 and 7, some or all of the example system 100and/or some or all of the example system 300 may be implemented using adevice such as the device 600 of FIG. 12. For example, the codecompressor 124, the code reorderer 128, and/or the code compressor 304could be implemented by the device 600. Similarly, the compiler 112and/or the linker 120 could be implemented by the device 600. As justone example, a computer program for implanting the code compressor 124,at least in part, could be stored in the non-volatile memory 612 andexecuted by the processor 604.

Referring again to FIGS. 2, 3, and 8 some or all of each of the examplemethods 160, 200, and 350 may be implemented using a device such as thedevice 600 of FIG. 12. For example, a computer program for implementingone or more of the blocks 164, 168, 172, and 176 of FIG. 2 could bestored in the non-volatile memory 612 and executed by the processor 604.

Referring again to FIGS. 4-6 and 9 some or all of each of the exampleroutines 220, 240, 260, and 400 may be implemented using a device suchas the device 600 of FIG. 12. For example, a computer program forimplementing some or all of the routine 220 of FIG. 4 could be stored inthe non-volatile memory 612 and executed by the processor 604.

Referring again to FIG. 10, the processor 604 of FIG. 6 may or may notinclude a subsystem such as the subsystem 450. Referring again to FIG.11, the processor 604 may or may not be configured to implement a methodsuch as the method 500. If the processor 604 is configured to implementthe method 500, it may be implemented using any combination of hardware,software, firmware, etc.

A processor that includes a subsystem such as the subsystem 450 of FIG.10, and/or that is configured to implement a method such as the method500 of FIG. 11 may be used in a variety of systems, including systemsuch as the system 600 of FIG. 12. For example, such a processor couldbe used in a desktop computer, a laptop computer, a workstation, aserver, a mainframe, a personal digital assistant (PDA), a televisionset-top box, a portable communication device (e.g., a cellular phone, asatellite phone, a pager, etc.), embedded systems, etc.

Some or all of the blocks of FIGS. 1-3, 7, and 8, and the routines ofFIGS. 4-6 and 9 may be implemented using one or more software programs.Each such program may be for execution by a processor and may be storedon a computer readable medium such as one or more of a CD-ROM, a floppydisk, a hard drive, a digital versatile disk (DVD), a memory card, amemory stick, a read-only memory (ROM), a random-access memory (RAM), anerasable programmable ROM (EPROM), an electrically erasable programmableROM (EEPROM), a carrier wave signal, etc., or a memory associated withthe processor, but persons of ordinary skill in the art will readilyappreciate that the entire program or parts thereof could alternativelybe executed by a device other than a processor, and/or embodied infirmware and/or dedicated hardware in a well known manner. Further,although example methods and programs are described with reference toparticular flow diagrams and pseudocode, persons of ordinary skill inthe art will readily appreciate that many other methods and routines mayalternatively be used. For example, the order of execution of the blocksor pseudocode statements may be changed, and/or the blocks or pseudocodestatements may be changed, eliminated, or combined.

Similarly, some or all of the blocks of FIGS. 1, 7, 10-12 may bechanged, eliminated, or combined.

It is to be understood that the techniques described herein may becombined. For example, some or all of the techniques described withreference to FIGS. 1-6 may be combined with some or all of thetechniques described with reference to FIGS. 7-11.

While the invention is susceptible to various modifications andalternative constructions, certain illustrative embodiments thereof havebeen shown in the drawings and are described in detail herein. It shouldbe understood, however, that there is no intention to limit thedisclosure to the specific forms disclosed, but on the contrary, theintention is to cover all modifications, alternative constructions andequivalents falling within the spirit and scope of the disclosure asdefined by the appended claims.

1. A method for reducing code size, the method comprising the acts of:identifying a replaceable subset of instructions at a first locationwithin a set of instructions and a matching target subset ofinstructions at a second location within the set of instructions;determining a base offset and a relative offset, wherein the base offsetand the relative offset indicate an absolute offset from the firstlocation to the second location; inserting, prior to the first location,an instruction to cause a base offset storage element to be loaded withthe base offset; and replacing the replaceable subset of instructionswith a second instruction to cause a program counter to be modifiedbased on the relative offset and a value in the base offset register,wherein the modified program counter indicates the second location.
 2. Amethod according to claim 1, further comprising the act of choosing thetarget subset of instructions from a plurality of candidate targetsubsets of instructions at different locations.
 3. A method according toclaim 2, wherein the act of choosing the target subset of instructionscomprises at least one of A, B, and C: A) determining sizes of candidatesecond instructions to replace the replaceable subset of instructions,each candidate second instruction to cause the program counter to bemodified to indicate the location of the corresponding candidate targetsubset of instructions; and  choosing the target subset of instructionsfrom the plurality of candidate target subsets based on the sizes of thecandidate second instructions; B) determining respective absoluteoffsets between the first location and the locations of the plurality ofcandidate target subsets; and  choosing the target subset ofinstructions from the plurality of candidate target subsets based on thedetermined absolute offsets; C) choosing the target subset ofinstructions from the plurality of candidate target subsets based on thewhether candidate target subsets are located in regions of frequentlyexecuted code.
 4. A method according to claim 1, wherein determining thebase offset and the relative offset comprises: determining the absoluteoffset from the first location to the second location; determining thebase offset based on the absolute offset; and determining the relativeoffset based on the absolute offset and the base offset.
 5. A methodaccording to claim 4, wherein determining the relative offset comprisessubtracting the base offset from the absolute offset.
 6. A methodaccording to claim 4, further comprising: identifying a plurality ofreplaceable subsets of instructions at respective first locations and aplurality of respective matching target subsets of instructions atrespective second locations; determining a plurality of absolute offsetsfrom the respective first locations to the respective second locations;determining the base offset based on the plurality of absolute offsets;and determining a plurality of relative offsets based on the pluralityof absolute offsets and the base offset.
 7. A method according to claim6, wherein determining the plurality of relative offsets comprisessubtracting the base offset from each absolute offset of the pluralityof absolute offsets.
 8. A method according to claim 4, wherein replacingthe replaceable subset of instructions with the second instructioncomprises: replacing the replaceable subset of instructions with a thirdinstruction to cause the program counter to be modified based on theabsolute offset, wherein the modified program counter indicates thesecond location; and replacing the third instruction with the secondinstruction.
 9. A method according to claim 1, further comprising theact of reordering at least some portions of the set of instructions toattempt to reduce the absolute offset.
 10. A computer readable mediumhaving stored thereon machine executable instructions, the machineexecutable instructions capable of causing the machine to: identify areplaceable subset of instructions at a first location within a set ofinstructions and a matching target subset of instructions at a secondlocation within the set of instructions; determine a base offset and arelative offset, wherein the base offset and the relative offsetindicate an absolute offset from the first location to the secondlocation; insert, prior to the first location, an instruction to cause abase offset storage element to be loaded with the base offset; andreplace the replaceable subset of instructions with a second instructionto cause a program counter to be modified based on the relative offsetand a value in the base offset register, wherein the modified programcounter indicates the second location.
 11. A computer readable mediumaccording to claim 10, the machine executable instructions capable ofcausing the machine to choose the target subset of instructions from aplurality of candidate target subsets of instructions at differentlocations.
 12. A computer readable medium according to claim 10, themachine executable instructions capable of causing the machine to:determine the absolute offset from the first location to the secondlocation; determine the base offset based on the absolute offset; anddetermine the relative offset based on the absolute offset and the baseoffset.
 13. A computer readable medium according to claim 10, themachine executable instructions capable of causing the machine toreorder at least some portions of the set of instructions to attempt toreduce the absolute offset.
 14. A system for compressing computerexecutable code, the system comprising: a first computer readable mediumto store a set of instructions to be compressed; a second computerreadable medium; a processor coupled to the first computer readablemedium and the second computer readable medium, the processor configuredaccording to executable instructions stored on the second computerreadable medium to: identify a replaceable subset of instructions at afirst location within the set of instructions stored on the firstcomputer readable medium and a matching target subset of instructions ata second location within the set of instructions, determine a baseoffset and a relative offset, wherein the base offset and the relativeoffset indicate an absolute offset from the first location to the secondlocation, insert, prior to the first location, an instruction in the setof instructions stored on the first computer readable medium to cause abase offset storage element to be loaded with the base offset, andreplace the replaceable subset of instructions with a second instructionto cause a program counter to be modified based on the relative offsetand a value in the base offset register, wherein the modified programcounter indicates the second location.
 15. A system according to claim14, wherein the first computer readable medium comprises the secondcomputer readable medium.
 16. A system according to claim 14, furthercomprising a third computer readable medium to store source code;wherein the processor is configured according to executable instructionsstored on the second computer readable medium to compile at least someof the source code to generate the set of instructions stored on thefirst computer readable medium.
 17. A system according to claim 16,wherein the first computer readable medium comprises the third computerreadable medium.
 18. A system according to claim 16, wherein theprocessor is configured according to executable instructions stored onthe second computer readable medium to generate machine readableinstructions based on the set of instructions stored on the firstcomputer readable medium.
 19. A system according to claim 14, furthercomprising a third computer readable medium to store assembly languagecode; wherein the processor is configured according to executableinstructions stored on the second computer readable medium to assembleat least some of the assembly language code to generate the set ofinstructions stored on the first computer readable medium.
 20. A systemaccording to claim 19, wherein the first computer readable mediumcomprises the third computer readable medium.
 21. A method for executinga computer program, the method comprising the acts of: in response to afirst instruction, setting a base offset storage element of a processorwith a value; in response to a second instruction that indicates arelative offset and a length, modifying a program counter of theprocessor based on the value in the base offset register and therelative offset; executing a number of instructions starting at a secondlocation indicated by the program counter modified in response to thesecond instruction, wherein the length indicates the number ofinstructions; after executing the number of instructions starting at thesecond location, modifying the program counter to point to a thirdinstruction adjacent to and subsequent to the second instruction.
 22. Amethod according to claim 21, further comprising: in response to thefirst instruction, selecting one base offset storage element from aplurality of base offset storage elements of the processor, the firstinstruction indicating the one base offset storage element; in responseto the first instruction, loading the selected base offset storageelement with the value; in response to the second instruction, selectingthe one base offset storage element from the plurality of base offsetstorage elements of the processor, the second instruction indicating theone base offset storage element; in response to the second instruction,modifying the program counter of the processor based on the value in theone base offset register and the relative offset.
 23. A method accordingto claim 21, further comprising determining a third location of thethird instruction in response to the second instruction; whereinmodifying the program counter to point to the third instructioncomprises loading the third location into a storage element to store theprogram counter.
 24. A method according to claim 21, comprising at leastone of: subtracting the relative offset and the base offset from acurrent program counter value in response to the second instruction; andadding the relative offset and the base offset to a current programcounter value in response to the second instruction.
 25. A methodaccording to claim 21, wherein the first instruction comprises an opcodeand a first parameter, the first parameter to indicate the base offset.26. A method according to claim 25, wherein the first instructionfurther comprises a second parameter to indicate one of a plurality ofbase offset storage elements.
 27. A method according to claim 26,wherein the opcode of the first instruction indicates one of a pluralityof base offset storage elements.
 28. A method according to claim 21,wherein the second instruction comprises an opcode, a first parameter,and a second parameter, the first parameter to indicate the relativeoffset and the second parameter to indicate the length.
 29. A methodaccording to claim 28, wherein the second instruction further comprisesa third parameter to indicate one of a plurality of base offset storageelements.
 30. A method according to claim 28, wherein the opcode of thesecond instruction indicates one of a plurality of base offset storageelements.
 31. A processor, comprising: a base offset storage element; aprogram counter storage element; an adder having a first input coupledto the base offset storage element, a second input coupled to receive avalue stored in the program counter storage element, and an outputcoupled to the program counter storage element; an instruction decodeunit coupled to base offset storage element and to the program counterstorage element, the instruction decode unit also coupled to a thirdinput of the adder, the instruction decode unit configured to: cause abase offset to be loaded into the base offset storage element inresponse to a first instruction that indicates the base offset, cause arelative offset to be coupled to the third input of the adder inresponse to a second instruction that indicates the relative offset, andcause the output of the adder to be stored in the program counterstorage element.
 32. A processor according to claim 31, wherein theadder is configured to, at least one of: subtract the first input andthe third input from the second input; and add the first input, thesecond input, and the third input.
 33. A processor according to claim31, further comprising a multiplexer to selectively couple the baseoffset storage element to the first input of the adder; wherein theinstruction decode unit is configured to cause the multiplexer toselectively couple the base offset storage element to the first input ofthe adder in response to the second instruction.
 34. A processoraccording to claim 33, further comprising a plurality of base offsetstorage elements selectively coupled to the first input of the adder viathe multiplexer; wherein the instruction decode unit is configured tocause the base offset indicated by the first instruction to be loadedinto a first one of the base offset storage elements in response to thefirst instruction, the first instruction indicating the first one of theplurality of base offset storage elements. wherein the instructiondecode unit is configured to cause the multiplexer to selectively couplea second one of the plurality of base offset storage elements to thefirst input of the adder in response to the second instruction, thesecond instruction indicating the second one of the plurality of baseoffset storage elements.
 35. A processor according to claim 31, whereinthe processor comprises at least one of a complex instruction setcomputer (CISC) processor, a reduced instruction set computer (RISC)processor, an explicitly parallel instruction computing (EPIC)processor, a very long instruction word (VLIW) processor, a micro signalarchitecture (MSA) processor, a digital signal processor (DSP), and apipelined processor.
 36. A computing system, comprising: a hard diskstoring a set of executable instructions; a processor coupled to thehard disk, the processor comprising: a base offset storage element; aprogram counter storage element; an adder having a first input coupledto the base offset storage element, a second input coupled to receive avalue stored in the program counter storage element, and an outputcoupled to the program counter storage element; an instruction decodeunit coupled to base offset storage element and to the program counterstorage element, the instruction decode unit also coupled to a thirdinput of the adder; wherein the instruction decode unit is configuredto: cause a base offset to be loaded into the base offset storageelement in response to a first instruction that indicates the baseoffset, cause a relative offset to be coupled to the third input of theadder in response to a second instruction that indicates the relativeoffset, and cause the output of the adder to be stored in the programcounter storage element in response to the second instruction.
 37. Acomputing system according to claim 36, further comprising a bus tocouple the hard disk to the processor.
 38. A computing system accordingto claim 36, further comprising a computer readable medium coupled tothe processor, the computer readable medium comprising at least one of aCD-ROM, a floppy disk, an additional hard drive, a digital versatiledisk (DVD), a memory card, a memory stick, a read-only memory (ROM), arandom-access memory (RAM), an erasable programmable ROM (EPROM), and anelectrically erasable programmable ROM (EEPROM).
 39. A computer readablemedium having stored thereon machine executable instructions, themachine executable instructions comprising: a first instruction at afirst location having a relative offset parameter and a lengthparameter, the first instruction configured to: cause a processor tomodify a program counter based on the relative offset parameter and avalue stored in a base offset storage element, cause the processor toexecute a number of instructions starting at a second location indicatedby the program counter modified in response to the first instruction,wherein the length parameter indicates the number of other instructions,and cause the processor to, after executing the number of instructionsstarting at the second location, modify the program counter to point toa third instruction adjacent to and subsequent to the secondinstruction.
 40. A computer readable medium according to claim 39,further comprising a second instruction having a base offset parameter,the second instruction configured to cause the processor to load thebase offset storage element with the base offset parameter.
 41. Acomputer readable medium according to claim 40, wherein the secondinstruction is configured to load one of a plurality of base offsetstorage elements with the base offset parameter, wherein the secondinstruction indicates the one base offset storage element.
 42. Acomputer readable medium according to claim 41, wherein the secondinstruction includes at least one of a base offset storage elementparameter that indicates the one base offset storage element, and anopcode that indicates the one base offset storage element.
 43. Acomputer readable medium according to claim 39, wherein the firstinstruction is configured to cause the processor to modify the programcounter based on the relative offset parameter and the value stored inone of a plurality of base offset storage elements, wherein the firstinstruction indicates the one base offset storage element.
 44. Acomputer readable medium according to claim 43, wherein the firstinstruction includes at least one of a base offset storage elementparameter that indicates the one base offset storage element, and anopcode that indicates the one base offset storage element.